1. Field of the Invention
The present invention relates to a driving method to be employed for display apparatuses and display panels, more particularly to a display panel configured so as to carry out a subtractive color processing upon driving its display panel that employs the delta arrangement, as well as a driving technique to be employed for the display panel configured such way.
2. Description of Related Art
The stripe arrangement and the delta arrangement are the two methods employed most frequently for disposing sub-pixels in each pixel in LCD (liquid crystal display) panels. FIG. 1 shows a configuration of an LCD panel that employs the stripe arrangement and FIG. 2 shows a configuration of an LCD panel that employs the delta arrangement.
As shown in FIG. 1, in case of the LCD panel that employs the stripe arrangement, one pixel consists of three sub-pixels that represent red (R), green (G), and blue (B) colors respectively and are disposed side by side in a line in the horizontal direction. The same color sub-pixels are disposed linearly and adjacently in the vertical direction. In the following description, red, green, and blue sub-pixels will be referred to as R sub-pixels, G sub-pixels, and B sub-pixels respectively. In case of the stripe arrangement, each pixel consisting of three sub-pixels (R, G, and B sub-pixels) is square in shape.
On the other hand, as shown in FIG. 2, in case of the LCD panel that employs the delta arrangement, each pixel consists of an R sub-pixel, a G sub-pixel, and a B sub-pixel that are disposed to form a triangle and the center of each of those sub-pixels is positioned at the peak of such a triangle. Furthermore, in case of the LCD panel that employs the delta arrangement, each pixel is disposed over two lines. In case of the LCD panel that employs the delta arrangement, same color sub-pixels are disposed side by side in a zigzag pattern. For example, in case of the G sub-pixels on the first line and the G sub-pixels on the second line that is adjacent to the first line, the G sub-pixels on the second line are shifted from the G sub-pixels on the first line by one and a half sub-pixels in the horizontal direction. This is similar to the red and blue sub-pixels. In case of the LCD panel that employs the delta arrangement, the three sub-pixels (R, G, and B sub-pixels) disposed side by side in the horizontal direction come to form a rectangle in a general view and this point in the delta arrangement differs from the stripe arrangement.
Note that, however, same color sub-pixels are connected to one data line even in case of the delta arrangement. For example, in case of the disposition example shown in FIG. 2, the G sub-pixels of G2, G3, and G1 are connected to a common data line and no R and B sub-pixels are connected to the data line. Similarly, the G sub-pixels of G4, G7, and G5 are connected to another common data line and no E and B sub-pixels are connected to the data line.
Upon driving an LCD panel, a subtractive color processing is carried out for display data in some cases regardless of the pixel arrangement method (delta or stripe) employed for the display panel. The subtractive color processing means a processing that generates n-bit subtractive color image data (n<m) from the original m-bit image data without degrading the image as far as possible. This processing is employed widely to realize multilevel gradation display by getting over hardware restrictions.
There is another method employed most widely; it is the error diffusion processing. The error diffusion processing uses an algorithm that determines the subtractive color image data of an object sub-pixel according to an error between input image data of another sub-pixel adjacent to the former sub-pixel and the subtractive color image data. For example, the algorithm is disclosed by JP-A-09-090902, JP-A-2002-162953, JP-A-2002-251173, and JP-A-2002-258805, respectively. FIG. 3 shows an example of a subtractive color processing circuit that carries out an error diffusion processing to generate 6-bit subtractive color image data Dfrc from 8-bit input image data Din. The subtractive color processing circuit shown in FIG. 3 generates the subtractive color image data Dfrc of a single sub-pixel in one clock cycle of the dot clock signal DCL.
The subtractive color processing circuit shown in FIG. 3 includes addition circuits 101 and 102, a D latch circuit 103, a selector circuit 104, and an initial value setting circuit 105. The D latch circuit 103 holds the error Derr of an object sub-pixel. The initial value setting circuit 105 supplies the initial value DerrINI of the error used in an error diffusion processing. The initial value setting circuit 105 holds a frame count denoting the number of an object frame to be subjected to a subtractive color processing and a line count denoting the number of an object line. The initial value DerrINI generated by the initial value setting circuit 105 differs among frames and lines respectively.
The subtractive color processing circuit shown in FIG. 3 operates as follows.
At first, the selector 104 supplies either the initial value DerrINI generated by the initial value setting circuit 105 or the error Derr held in the D latch 103 to the addition circuit 102 according to the initial error value read signal DE_POS. Concretely, in the error diffusion processing for the first sub-pixel of each line to be processed, “1” is set in the initial error value read signal DE_POS, so that the selector 104 supplies the initial value DerrINI to the addition circuit 102. On the other hand, in the error diffusion processing for each of other sub-pixels, “0” is set in the initial error value read signal DE_POS, so that the selector 104 supplies the error Derr held in the D latch 103 to the addition circuit 102.
The addition circuit 102 adds up the lower-order 2 bits of the input image data Din and the error Derr (or the initial value DerrINI) to obtain a carry output cry and an error DerrN used in the error diffusion processing for a sub-pixel from which the next subtractive color image data Dfrc is calculated. The D latch 103 is triggered by the dot clock signal DLC to latch the error DerrN output from the addition circuit 102 and update the error Derr. The addition circuit 101 adds up the upper-order 6 bits of the input image data Din and the carry output cry of the addition circuit 102 to generate the subtractive color image data Dfrc of the object sub-pixel.
The error diffusion processing that generates the subtractive color image data Dfrc such way depends on the original image data, thereby causing the position of each high luminance sub-pixel to be changed. This is why the processing can suppress the generation of peculiar patterns that might cause screen flickering.